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video_compression_systems.tar
关于MPEG压缩的程序,里面有较多的源代码和完整的说明是用MICROBLAZE完成的。(On the MPEG compression process, there are more source code and complete description is completed with MicroBlaze.)
- 2008-06-13 22:23:45下载
- 积分:1
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Using VHDL realize the divider, so very, simulation adopted
用VHDL实现的除法器,非常好使,仿真通过了-Using VHDL realize the divider, so very, simulation adopted
- 2023-06-11 22:15:03下载
- 积分:1
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zidongmen1
控制步进电机转动,正反转,旋转角度完美掌握。很好用,亲测(Control stepping motor rotation, positive and negative rotation, perfect control of rotation angle. Very easy to use, personal test)
- 2018-12-25 16:41:07下载
- 积分:1
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Simulate
FPGA控制AD逐点采集信号,并将AD转换后的数据串行发送出去。(FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.)
- 2021-04-14 21:08:55下载
- 积分:1
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课程设计-数字钟
说明: 具有计时 设置时间 闹钟 秒表 功能的数字钟设计 外设矩阵键盘(Digital clock design peripheral matrix keyboard with the function of timing setting time alarm clock stopwatch)
- 2020-05-18 17:11:07下载
- 积分:1
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spi_hello
SPI接口测试程序,Xilinx参考设计,ML507硬件测试通过.(SPI interface test code,Xilinx reference design,tested on ML507 platform.)
- 2013-09-01 09:37:04下载
- 积分:1
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verilog ADPLL file with testbench
verilog ADPLL file with testbench
- 2022-04-20 22:45:21下载
- 积分:1
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基于VHDL语言的解码汉明编码,其中包含子
基于VHDL语言的汉明码的译码,含有校正子跟纠错检错功能-Based on the VHDL language decoding Hamming Code, which contains sub-calibration error with error correction function
- 2022-08-11 19:51:06下载
- 积分:1
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shizhong
VHDL写时钟,分频模块什么,实现计时。定点报时,定点闹钟,显示年月日。(verilog HDL)
- 2014-01-09 18:29:40下载
- 积分:1
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vivado_LED_Flow
本例程使用vivado2014.4工具,利用xilinx Basys3 实验板实现板载流水灯的两种模式控制。(This project uses verilog HDL to realize the the control of 16 leds loaded on Xilinx Basys3 board.)
- 2016-04-19 10:19:07下载
- 积分:1