各种常用模块的VHDL描叙实例，PDF格式

步进电机控制程序，用vhdl实现。可实现电机的正反转控制-Stepper motor control program, using vhdl implementation. Positive inversion of motor control can be realized

有自己制作的下载器原理图，包含了stlinkv2,XDS100V3,USBBLASTER.原理图和封装，一款多功能下载器。(Have their own production downloader schematic diagram, contains stlinkv2, XDS100V3, USBBLASTER. Schematic diagram and encapsulation, a multi-function downloader.)

vmm log 验证平台，采用vmm搭建 (vmm log verification platform, built by vmm)

代码为ahb interface ，用verilog编写的,包括仿真和综合。(Code for the interface AHB, written in Verilog, including simulation and synthesis.)

6264是一种8K×8的静态存储器.SRAM 的典型芯片有2KB 的6116、8KB 的6264 以及32KB的62256,其中6264 芯片应用最为广泛.(6264 is the 62256 typical chip SRAM.SRAM a 8K* 8 with 2KB 6116, 8KB 6264 and 32KB 6264 chip, which is most widely used. )

说明：  isa MEMORY PLAN eu biu asm

saa7113_配置.SAA7113视频解码系列芯片的一种，8位彩色配置(saa7113_ configuration. SAA7113 video decoder chips in an 8-bit color configuration)

基于FPGA设计ADC0809采样控制器原代码-FPGA-based design ADC0809 Sampling Controller source

此代码是SPI接口的Master的Verilog源代码，经上板测试是没有问题的，请大家放心使用 (This code SPI Interface Master of Verilog source code, there is no problem on board test, please rest assured to use)

ALTERA上DE2平台，利用内部50M Hz时钟，在数码管模拟显示时间(时分秒)。-ALTERA on DE2 platform, using internal 50M Hz clock, in the digital control simulation show time (hours minutes and seconds).