超大规模集成电路的VHDL基本编码…………

此代码可以实现16位二进制和BCD码之间的转换。(This code can realize the conversion between 16 bit binary and BCD code.)

适应多个模式的rs编码，Verilog，选择对应的多项式(RS coding adapted to multiple modes.)

VHDL编写的数字钟，在Q-ii下编译，实现闹铃设置与定时闹铃，分时秒显示-VHDL prepared digital clock, in the Q-ii under the compiler to achieve regular alarm and alarm settings, time-seconds display

基于VHDL的LCD显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the LCD display program, including complete source code, locking pin, as well as download files documents can be directly downloaded using

FPGA的fifo与dsp的emif接口测试程序(EMIF interface test program for FIFO and DSP of FPGA)

二进制转十进制BCD码 Verilog语言 quartusII(Binary to decimal BCD code Verilog language quartusII)

说明：  用VHDL实现密码锁功能，用状态机实现，分管理员和用户两种功能，可分别修改密码，重置密码等。(codelock，VHDL，state)

说明：  基于fpga的ad采样程序 可控制ad9226对信号进行采样(Ad9226 signal sampling can be controlled by ad9226 sampling program based on FPGA)

TASKS OF TWO TYPES CAN BE RUN FOR EVERY 2 MIN.

用VHDL语言实现的ARM处理器的标准内核的源代码程序，可在重用-use of the VHDL standard ARM processor core source code procedures, the reuse