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vivado 从此开始配套资料
vivado入门使用介绍,初学者入门学习(vivado Instructional pdf)
- 2020-07-04 18:00:01下载
- 积分:1
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rs_enc
Verilog code for RS-(255,239) encoder.
- 2021-04-06 16:19:02下载
- 积分:1
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有关FPGA芯片的管脚的封装的一些资料。
有关FPGA芯片的管脚的封装的一些资料。-Pin on the FPGA chip packaging some of the information.
- 2023-06-26 06:30:03下载
- 积分:1
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内容1:哈尔滨工程大学信息与通信工程学院的课件
内容1:哈尔滨工程大学信息与通信工程学院的课件-适合初学VHDL语言的人。内容2:VHDL语言详解的讲义。-1: Harbin Engineering University College of Information and Communication Engineering of software- suitable for novice VHDL language. Content 2: VHDL language of the notes explain.
- 2023-08-22 14:50:04下载
- 积分:1
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these files are written in verilog but i am uploading in text format
these files are written in verilog but i am uploading in text format
- 2022-02-06 16:09:07下载
- 积分:1
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PCI-based--DSG
基于PCI的数字信号发生器
关键词:PCI总线,PCI9054,FPGA,卡尔曼滤波器(PCI-based digital signal generator
Keywords: PCI bus, PCI9054, FPGA, Kalman filter)
- 2016-06-12 20:41:45下载
- 积分:1
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VHDL-TESTBENCH
VHDL TESTBENCH书写规范,对学习FPGA的同学很有帮助,掌握仿真语言书写规范。(VHDL TESTBENCH description of the norms, the students learn FPGA helpful, master the language of simulation techniques)
- 2016-12-15 21:33:24下载
- 积分:1
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Block-cipher-lock
密码锁verilog源代码,包括四个七段数码管显示模块,设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)
- 2014-01-11 23:57:19下载
- 积分:1
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verilog2
Learning Verilog Chinese Version Part 2
- 2012-06-15 03:24:15下载
- 积分:1
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xilinx-timing-constrains
ISE时序约束笔记——Global Timing Constraints,这个文档中详细介绍了如何使用ISE中约束工具和原理,对fpga水平提高有很大帮助(In this file , global timing constraints is introduced very clearly. It can really helps)
- 2012-04-16 11:08:45下载
- 积分:1