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package_control-master
从github下载的,能够参考设计AXI4的协议接口(AXI4 Verilog template)
- 2019-03-30 16:14:05下载
- 积分:1
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io_uart
verilog设计的32位IO口扫描后通过串口发送到计算机(Verilog design of 32 bit IO export after scanning through the serial port to the computer)
- 2012-12-27 00:05:01下载
- 积分:1
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zidongmen1
说明: 控制步进电机转动,正反转,旋转角度完美掌握。很好用,亲测(Control stepping motor rotation, positive and negative rotation, perfect control of rotation angle. Very easy to use, personal test)
- 2018-12-25 16:41:07下载
- 积分:1
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er
秒表 东北大学秦皇岛分校 电子设计自动化 实验(Stopwatch Northeastern University at Qinhuangdao electronic design automation experiment)
- 2012-06-27 02:25:14下载
- 积分:1
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ad9467_config1
说明: 采用Verilog编写AD9467配置文件(Using Verilog to write ad9467 configuration file)
- 2020-07-03 15:40:02下载
- 积分:1
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FSM_Robustness_Testing
基于有限状态机的健壮性测试研究。
关键词:健壮性测试;增强有限状态机;全球平台;安全通道协议(The Research of Robustness Testing Based on FSM)
- 2012-09-06 14:08:56下载
- 积分:1
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bubblesort1024ram
说明: 快速冒泡排序基于FPGA实现,有测试文件以及设计图,实现1024*32位数序的多数排序,突破传统是的REG类型少数排序,利用RAM,针对RAM中的无序数的地址调换,达到排序目的,仅供学习交流(Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking tradition is a REG types of minority sorting, the use of RAM, the disorder for the RAM address of the number of exchange, to sort purpose, only to learn the exchange of.)
- 2010-03-24 15:19:50下载
- 积分:1
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mybch1
说明: 实现(7,4)BCH码的编码和译码。已知生成矩阵和校验矩阵,通过c=m*G进行编码,译码时利用伴随式译码。s=c*H‘,求得伴随式,对应的错误图样找到错误位置,对错误位置进行更正,得到译码结果。(Coding and decoding of (7,4) BCH Codes)
- 2021-04-27 17:28:44下载
- 积分:1
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Tutorial.tar
zedboard partial reconfiguration tutorial
- 2015-04-08 01:32:35下载
- 积分:1
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bayer_3RGB_interpolation
一个基于FPGA用verilogHDL设计的bayer格式转RGB格式的模块,本人设计(a code used for bayer_3RGB_interpolation ,which based on FPGA by verilogHDL)
- 2011-12-25 21:58:05下载
- 积分:1