实践 tic tac toe vga

Verilog实现按键消抖，工程，已下板验证通过。(Verilog achieves keystroke jitter elimination. The project has been validated on the lower board.)

说明：  基于数据通路和控制器的高校简单PPM设计(PPM design based on datapath and controller)

VHDL汇编语言原理及源代码。spartan 3e开发板试用。(VHDL language.)

Interface for ADS8361 TI ADC IP Core for ALTERA NIOS2

verilog产生高斯白噪声，gwn_en信号产生使能，gdata是幅度服从高斯分布，功率谱密度为定值的高斯白噪声序列，共10位（现实中只能够做到带限，跟dac输出带宽有关，我的系统只能做到300kHz）(verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence value, a total of 10 (in reality can only be band-limited, with dac output bandwidth related, My system can do 300kHz))

RS通用编码器，根据定义的参数以及本原多项式就能实现各种体制的编码，Verilog实现，还附带有限域乘法的实现，代码清晰，精炼

伪随机LED灯，实现八位LED灯的随机闪烁以及其它的控制。(Pseudo-random LED lamp)

说明：  用VHDL语言设计一个校验器，用for loop实现8位数据的偶校验，(With a for loop to achieve 8-bit data parity)

说明：  用于FPGA中zynq的温度上报，通过逻辑方式。(It is used to report the temperature of zynq in FPGA by logic)

Testbench 不仅要产生激励也就是输入，还要验证响应也就是输出。当然也可以只产生 激励，然后通过波形窗口通过人工的方法去验证波形，这种方法只能适用于小规模的设计(The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce Incentive, and then the waveform by the waveform window by artificial means to verify, this method is only applicable to small-scale design)