这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器

说明：  之前一直找不到自学编写了一个，PID案例，分享下(I have been unable to find a self-taught, compiled a PID case, share under)

FPGA驱动MT9M001的verilog代码，里面还有ddr3部分将图像数据进行存储，lcd进行图像显示，里面的摄像头驱动部分很详细，大家可以多研习研习(Verilog driver MT9M001 code, which is also the DDR3 image data storage, LCD display, which drives the part is very detailed, we can learn more)

实现基于FPGA的vga显示，亲测能编译得过，不同开发版应该要相应改动（PS: 不太了解）

使用verilog写的频率计，可切换档位(Frequency counter using verilog write switch stalls)

说明：  为串口收发器以及汉明编码，将电脑通过串口发送的7位数据转化成汉明码显示于led上，或把接收到的11位汉明码解码并验错纠错(For the serial port transceiver, and Hamming codes, the computer through the serial port into 7-bit data displayed on the led on the Hamming code, or to receive the 11 Hamming code error correction decoding and experience)

DS18B20温度传感器，用verilog语言实现(DS18B20 temperature sensor, with the verilog language)

模拟SDH帧结构，设计了状态机，能从连续传输的SDH字节流中找出帧头；从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟；设计了输入信号，输出包括E2串行数据、E2串行时钟和SDH帧头位置指示

48阶FIR滤波器的verilog，包含测试文件(48-order FIR filter verilog, including test paper)

dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies

多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)