这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器

booth algotihm verilog design and test

设计一个可编程间隔定时器，完成8253的功能，实现以下几点要求： 1、 含有3个独立的16位计数器，能够进行3个16位的独立计数。 2、 每一种计数器具有六种工作模式。 3、 能进行二进制/十进制减法计数。 4、 可作定时器或计数器。 -The design of a programmable interval timer, 8253 to complete the function, realize the following requirements: 1, contains three independent 16-bit counter, capable of three independent 16-bit count. 2, each with six counter mode. 3, can be binary/decimal subtraction count. 4, can be used for the timer or counter.

串口中断＿niosII.rar 解压密码：www.21control.com

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现对一个十字路口的交通灯的控制，包括4个红绿灯和4个2位的数码倒计时器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board to realize a crossroads traffic lights control, including four traffic lights, and four 2-bit digital countdown device.

比较详细的阐述了图像压缩的原理,并基于DSP和VHDL实现该系统,最后在FPGA上通过.(More detailed exposition of the principles of image compress, and VHDL-based implementation of the system, and finally in the FPGA.)

数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on

基本的VHDL程序本rar文件。 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

Testbench 不仅要产生激励也就是输入，还要验证响应也就是输出。当然也可以只产生 激励，然后通过波形窗口通过人工的方法去验证波形，这种方法只能适用于小规模的设计(The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce Incentive, and then the waveform by the waveform window by artificial means to verify, this method is only applicable to small-scale design)

Verilog学习例程EP2C5，内有跑马灯等18个程序(Verilog learning routines EP2C5, marquees and other 18 programs)

FPGA应用举例，非常适合初学者，高手莫下-FPGA application, for example, very suitable for beginners, experts, under Mo