that I wrote four string and turn ISE code In xilinx Spartan3E debugging has bee...

libero soc工程，实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)

该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。(The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, including PC, the USB firmware, drivers, FPGA' s Communication Program)

4X4电子密码锁的中央控制系统。控制6位输入。-4x4 electronic locks central control system. Six input control.

说明：  在FPGA内，实现PS2键盘数据读取功能，verilog源代码(In the FPGA, achieving PS2 keyboard data read functions, verilog source code)

AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)

VHDL语言实现时钟程序，用fpga开发板试过后，能够执行-VHDL Pang Sung-wife of mother

数字化，宽带化，是当今无线通信的重点主流方向，FPGA以其功能强大，开发周期短，投资少，可重复修改，开发工具智能及软件可升级等特点成为无线通信首选。(Digital, broadband, is the focus of today s mainstream wireless communications, FPGA with its powerful, short development cycle, low investment, repeatable modify, intelligence and software development tools and other characteristics can be upgraded to become the first choice of wireless communication.)

编写 VHDL 代码为 4 x 1 多路复用器，使用下面的方法 (1) if else 语句 (2) case 语句 (3) 与声明

说明：  how to come ture a costas loop in FPGA with verilog,it is very useful on project

说明：  实现了从摄像头读取数据到液晶的显示，利用了cycloneV 和康欣的开发板资源(It realizes the display of reading data from camera to liquid crystal.)