VHDL implement serial port, it can communicate with pc, it can accept and send m...

此vhdl程序实现了在FPGA上构建UART通信串口。分为两部分，UART的发送端transfer和接收端receiver。需要外部根据需求提供波特率时钟。(This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the baud clock external demand.)

说明：  uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device

基于FPGA的PWM控制器设计，包含ADC0820模块，按键扫描，PID，PWM控制器等模块，VHDL语言完成，已仿真通过(PWM controller design based on FPGA, including ADC0820 module, key scan, PID, PWM controllers and other modules, VHDL language completed, through simulation)

基于Verilog的PCI总线接口的设计及应用-Verilog-based PCI-bus interface design and application.

本白皮书探讨了在PCI Express的因素 技术可能会影响性能。它还 提供指导如何估算 的系统性能。(This white paper explores the factors in PCI Express technology may affect performance. It also provides guidance on how to estimate the system performance.)

改程序将实现对两个信号的曼切斯特编码，以用仿真软件验证过了(Reform program will achieve two Manchester encoded signal to a validated using simulation software)

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

VHDL学习总结，简要概括了VHDL，非常适合做学习的总结-VHDL study conclusion, a brief summary of VHDL, very suitable for learning to do a summary of

Lights, Car light emulator for turn, stop and emergency

HDL verilog 电子密码锁 输入错误后有报警 输入正确后有提示(HDL Verilog electronic code lock input errors have prompted alarm input is correct)