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liyuanlnx_key_beep
说明: FPGA按键加蜂鸣器实验:
加延时防抖+蜂鸣器(Experiments of keys and buzzers in FPGA)
- 2020-06-22 04:00:01下载
- 积分:1
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McBSP_8bit_Asyn
基于FPGA的Mcbsp通信源码,经过项目实测检验(Mcbsp communication source code based on FPGA,Through the test of the project.)
- 2018-03-19 17:19:17下载
- 积分:1
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Verilog HDL系列和转换的准备。我用电流输出类型。股份有限公司...
Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.
- 2022-06-18 11:27:00下载
- 积分:1
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11-07-11
AD9910实现脉冲内线性调频信号,仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)
- 2013-09-16 10:52:00下载
- 积分:1
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FPGA
基于FPGA的VHDL编程实现各种音频信号,采用的是周立功公司的fusion_startkit开发板。-FPGA-based VHDL Programming realize a variety of audio signals, are used by companies fusion_startkit weeks Ligong development board.
- 2022-07-15 20:29:13下载
- 积分:1
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fleverDDS_new
fpga控制da产生幅值频率可调的正弦波程序(the fpga Control da produce the amplitude adjustable frequency sine wave program)
- 2013-01-07 10:47:43下载
- 积分:1
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verilog hdl教程135例:verilog hdl语言类似于C语言,便于学习。本文档带有源代码,9...
verilog hdl教程135例:verilog hdl语言类似于C语言,便于学习。本文档带有源代码,9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10
- 2022-08-15 23:59:39下载
- 积分:1
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CPUdesign
说明: 计算机组成原理实验多时钟周期CPU设计,包含VHDL代码的设计,实验电路图,实验详细截图。(Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.)
- 2020-09-07 19:28:05下载
- 积分:1
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BPSK
BINARY PHASE SHIFT KEYING
- 2014-08-20 17:35:44下载
- 积分:1
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FPGA开发全攻略
FPGA设计攻略及流程,包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)
- 2017-12-12 16:30:52下载
- 积分:1