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Xilinx FPGA make 50 smaller-Xilinx FPGA make 50 smaller

vhdl code for 8051 processor

VHDL硬件描述语言与数字逻辑电路设计,学习VHDL的好资料-VHDL hardware description language and digital logic circuit design, VHDL learning good information

说明：  用FPGA实现CNN算法，实现CNN加速(Realization of CNN Algorithms with FPGA)

de2开发板上的一个小程序 模60的计数器/分频器(de2 board developed a small program module 60 of the counter/divider)

资源描述该程序可以读写FAT32文件系统的SD卡。SD卡的接口现在采用IO模拟接口方式。在板子SD卡座上插上FAT32格式的SD卡，请连接下载线的JTAG接口到板子，下载fpga的SOF文件，再下载NIOSII IDE中的文件。

This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)

用VERILOG实现一个被除数为8位、除数为4位的高效除法器(With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider)

cyclone和cyclone2用在5v系统里使用方法,使得FPGA芯片在5V系统中兼容-cyclone and cyclone2 system used in the use 5v, making FPGA chip compatible with the 5V system

一个电子秒表，最大显示59.99,具有暂停和reset功能(An electronic stopwatch, the maximum display 59.99, with a pause and reset functions)