verilog实现的“六进制约翰逊计数器”。

Xapp 200 64 bit DDR SDRAM design files for Xilinx Vertix

硬件描述语言,verilog HDL,实现了解码器的设计-hardware description language, verilog HDL, the decoding of Design

基于FPGA的自治型SPWM波形发生器的设计！正弦脉宽调制（SPWM）技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用，如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈！-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit as the core of the power electronic devices have a wide range of applications, how to generate SPWM pulse sequence and its implementation means PWM technology is the key. Kazakhstan investigate everyone!

电子设计自动化中的计数器的实现程序，基于VHDL语言完成的-Electronic design automation in the realization of counter procedures, based on the VHDL language completed

本源码是用Verilog编写的12位移位相加乘法器的设计源码，开发软件为MAX+PLUS，已经测试通过。(The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.)

具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.

用VHDL硬件语言实现的iic顶层控制程序-Using VHDL hardware language to achieve the top level of the IIC control procedures

数字密码锁的vhdl实现，包括设置密码，修改密码，报警。

复旦cpu COS

Altera QUARTUS 7.2的矩阵键盘电子琴完整工程（含源码），在EP2C20芯片上实现-Altera QUARTUS 7.2 Project of matrix keyboard electronic organ, implement on EP2C20 chip.