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DLX-pipeline-in-verilog
verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)
- 2013-08-24 22:59:48下载
- 积分:1
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signal-processing-matlab
信号处理中所用到的matlab程序,包括LFM,NLFM,BPSK,QPSK等等。(Matlab procedures used in signal processing, including LFM, NLFM, BPSK, QPSK, and so on.)
- 2012-11-01 00:55:18下载
- 积分:1
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PCI_Master
pci协议主模块开发实用代码, 适合初级学习者使用 很不错(pci agreement to develop practical code, very good for junior learners)
- 2013-01-10 14:48:24下载
- 积分:1
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ar0134_1280x720P60
Camera AR0134详细的寄存器配置,以及配置顺序,可以用来初始化摄像头(Camera AR0134 detailed register configuration sequence )
- 2016-05-15 12:16:56下载
- 积分:1
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rs485_uart
fpga的RS485代码,非常容易,适合学习(the code of rs485 in fpga, very easy,suitable for learning)
- 2019-07-11 14:24:54下载
- 积分:1
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dec
A Dec example written in VHDL.
- 2009-09-23 08:57:25下载
- 积分:1
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elpiano
自己写的FPGA实现电子琴的VHDL程序,曲目是两只老虎,用到一些模块,和片内存储间,呵呵(FPGA realization of his keyboard to write the VHDL program, tracks are two tigers, a number of modules used, and on-chip storage room, huh, huh)
- 2020-12-28 01:39:02下载
- 积分:1
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01-USB
usb读取,仅供参考,在实际应用中要更改以下数据。(Read usb data)
- 2012-12-24 15:35:40下载
- 积分:1
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nor_flash_verilog
fpga verilog实现 S29GL256S 系列 并行 nor flash 的读写擦除操作功能。 verilog源代码。(Verilog S29GL256S to achieve FPGA series parallel flash nor read and write erase operation function. Verilog source code)
- 2021-04-15 16:18:54下载
- 积分:1
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篮球24秒可控计时器设计
用VHDL语言设计篮球24秒可控计时器功能说明:1.具有24秒计时、显示功能; 2.设置外部按键,完成清零、暂停、恢复控制; 3.24秒倒计时,时间间隔为1s; 4.时间到后发出报警信号,并在3s后解除。
- 2022-05-28 22:06:17下载
- 积分:1