USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言

说明：  libero soc工程，实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)

MATLAB Filter Design HDL Coder Simunlink HDL Coder Xilinx ISE Webpack

用VHDL实现视频控制程序(实现对图像的采集和压缩)-Using VHDL video control procedures (the achievement of the image acquisition and compression)

VHDL实现led灯的动态扫描，主要对CLK进行分频-VHDL realization led lamp dynamic scan, the main points of the CLK to the frequency

this is fpga based vhdl coding and report for wavlet based image compression in vhdl

以前在学校里的课程设计，使用verilog编写的一个CPU程序，可以下板子-Ago in the school curriculum design, the use of Verilog CPU prepare a procedure under the board

counter number one to nine after 1s

USB2.0的IP核开发.代码可以直接使用已经验证过(USB2.0 IP kernel development. Code can be used directly, has been verified)

HDB3编码器与解码器，以及RTL图，使用Verilog HDL实现(HDB3 encoder and decoder, and RTL diagram, use Verilog HDL to implement)

清华大学电子课程设计：Verilog，QuartusII可正确运行，可下载到FPGA上，音乐计算器，完成两个三位数的运算，有注释，很强大！！(Verilog, QuartusII run correctly, can be downloaded to the FPGA, music, calculator, completed two three-digit operations, there are notes, very powerful! !)