USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言

verilog标准语法，还有很多的样例参考，学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)

数字钟vhdl实现，在线测试无误，具有闹钟，对表功能(Digital clock vhdl implementation, online testing is correct, with alarm, the table function)

说明：  verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

说明：  控制步进电机转动，正反转，旋转角度完美掌握。很好用，亲测(Control stepping motor rotation, positive and negative rotation, perfect control of rotation angle. Very easy to use, personal test)

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

基于altera公司MAX10型FPGA的ADC调试程序(ADC-based debugger altera company MAX 10 type of FPGA)

说明：  这个事VHDL基础知识，内面主要内容是编码器的插V过程，值得下载学习！(it is really useful for those who never touch it!)

计算机组成原理课程实验使用软件，Thinpad教学机教学实验软件 实现mips代码到机器代码之间的转换 实现本机和FPGA板的通信，将机器代码送入 可在本机编写代码送入fpga板的sram中，fpga板的cpu会运行(Computer architecture course experiment using software, Thinpad teaching machine teaching experiment software mips code into machine code conversion for communication between the machine and the FPGA board can be fed into the machine code written in native code into the fpga board sram in, fpga board cpu runs)

crc5 bolck in usb contreoller

LMS算法自适应滤波器的Matlab仿真分析.(LMS matlab fangzhenchengxu.)