USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言

there are exemple in the vhdl

基于FPGA的门级逻辑实现快速乘法运算的verilog源程序。-FPGA-based gate-level logic implementation of rapid multiplication of the verilog source.

ML605评估板上的流水灯，可以实现每隔0.16秒进行+1操作 #include #include #include #include #include int main() {   char a[] = "-100" ;   char b[] = "123" ;   int c ;   c = atoi( a ) + atoi( b ) ;   printf("c = %d ", c) ;   return 0;

vhdl code for carry lookahead addder

基于VHDL+FPGA的神经网络设计，实现简单的字符识别(Design of Neural Network Based on VHDL+FPGA to Realize Simple Character Recognition)

说明：  使用vivado和Xilinx开发板实现抢答器，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to achieve the responder, the development board is Xilinx artix-7)

多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)

关于一个串行数据输入 根据时序将数据分两路输出的程序 (on a serial data input timing will be based on output data using two procedures)

SDIO slave verilog code

华为内部资料，关于FPGA设计的详细过程介绍，很不错的。本文档从FPGA器件结构出发以速度路径延时大小和面积资源占用率为主题描述在FPGA设计过程中应当注意的问题和可以采用的设计技巧。(Huawei internal information, with regard to detailed FPGA design process of introduction, it is good. This document from the FPGA device structure in order to speed the path delay and area the size of the theme of the occupancy rate of resource description in the FPGA design process should pay attention to the problems and design techniques can be used.)