在MAXPLUSII下实现BOOTH算法，可以进行任意位K×K的乘法

利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)

用VHDL编写的关于SCAN的一个小程序，希望大家看了后能喜欢，也可以学学哟！-VHDL SCAN prepared on a small procedures in the hope that after reading them you will like and can learn yo!

VHDL版的C51核(MC8051)-VHDL version of the C51 core (MC8051)

前导零的计算 (Calculation of leading zeros)

数字频率计 数字频率计-Digital frequency meter digital frequency meter

自己用verilog编写的urisc程序，调试成功，压缩包里有仿真图像，值得学习参考。(Written in verilog urisc program debugging, simulation image compression bag, worth learning reference.)

用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS--use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-

根据ASMD图设计验证冒泡排序算法。给出设计程序及时序仿真结果，含纸质报告。(According to the ASMD diagram design, verify the bubble sorting algorithm. Give the design procedure and the simulation result in time, including paper report.)

用verilog编程的TCON模块（时序控制器）的程序(Verilog programming module with TCON (timing controller) program)

卷积码（213）的编译码，VHDL语言编写的整个工程文件，带有仿真结果图。(Convolution code (213) codec, VHDL language of the whole project file with the simulation results shown in Fig.)