在nexys2数字cronometer

用fpga实现的连连看游戏，功能还不完善，不过可以借鉴。(Realize with FPGA Lianliankan game, function is not perfect, but can be used for reference.)

alter FPGA，包含sdram的nios系统开发实验完整工程文件-nios develop based nios IDE6.0，system involved an sdram

USB+FPGA电路设计原理图，实际的电路板运行正常，很有参考意义。-usb_sch

Bucknell Verilog Manual

altera的vga示例

Spartan 3E上的Rotary encoder控制程序，及验证它的小灯程序(Rotary encoder on the Spartan 3E control procedures, and verification procedures for its small light)

altera max10 USB demo，使用了phy，把开发板配置成U盘模式(altera max10 USB demo，using PHY device，design a U pan)

根据ASMD图设计验证冒泡排序算法。给出设计程序及时序仿真结果，含纸质报告。(According to the ASMD diagram design, verify the bubble sorting algorithm. Give the design procedure and the simulation result in time, including paper report.)

说明：  本代码是控制DS1302的VHDL代码，浅显易懂，方便修改，注意看data sheet，保证时钟和各个延迟满足要求即可(This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the various delays)