6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准...

Block LU decompostion of a matrix

8位有符号编码的整数基改性

传感信号无线数字传输系统的设计与实现.kdh(err)

层合板的刚度的计算和验算，包括拉伸刚度A、弯曲刚度D以及耦合刚度B。 首先要给定层合板的各个参数，具体有：层合板的层数N；各单层的弹性常数E1、E2、 、G12；各单层对应的厚度；各单层对应的主方向夹角 。(The stiffness of laminated plates is calculated and checked, including tensile stiffness, A, flexural stiffness, D and coupling stiffness B. First of all, it is necessary to give the parameters of laminated plates, such as the number of plies N, the elastic constants of each layer, E1, E2, and G12, the thickness of each monolayer, and the angle of the main direction corresponding to each single layer.)

此为数学形态滤波器消燥的代码，用于一维信号，涉及一个具体的例子，需要的话可以自己修改，修改相应的结构元素。(This is a mathematical morphology filter away dry code, used to one dimensional signal, involving a concrete example, necessary can change ourselves, change the structure of the corresponding elements)

RISC CPU IP CORE 可以用于直接的工程开发应用 有详细的说明书-RISC CPU IP CORE can be used to direct the development and application of the project has a detailed brochure

说明：  verilog语言书写，单周期CPU源码(single period CPU)

PCI的VHDL源码希望对大家有用！-PCI VHDL source hope useful for all!

i have coding for verilogHDL and VHDL. so please i want know that coding..

用硬件描述语言编程实现减法器,实现两个操作数的减法-Using hardware description language programming subtraction, and the achievement of the two operands of the subtraction