6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准...

实现ITU-BT1120数字并行接口的编码和解码(decode and encode ITU-BT1120 parallel digital interface)

包含一个ALU，实现斐波那契数列的计算。1.接受两个6位二进制输入。2.通过手动输入的时钟驱动每个周期进行一次计算。3.结果输出到led灯（使用NEXYS4开发板）(Including an ALU to realize the calculation of Fibonacci sequence. 1. Accept two 6-bit binary inputs. 2. Each cycle is driven by a clock input manually. 3. Output to LED lamp (using NEXYS4 development board))

基于FPGA的波束形成，包括ad转换，数据存储等部分。。(FPGA-based beamforming, including ad conversion, data storage and other parts. .)

16位有符号和无符号乘法器FPGA源代码(16-bit signed and unsigned multiplier FPGA source code)

it is a fir filter program VerilogHDL.(it is a filter program VerilogHDL fir.)

实现了QPSK的调制，使用了ise自带的dds的IP核(QPSK is modulated and the IP core of DDS is used in ise.)

Implement LMS vhdl code.

TI F28027 SCI 源码，中断，FIFO，LoopBack使能(TI F28027 SCI source code, interrupt, FIFO and Loopback enalbe)

收集的关于数字锁相环的理论模型和分析讨论，适用于FPGA的数字电路设计。(Theoretical models and analysis and discussion about digital PLL collected for FPGA-based digital circuit design.)

Xilinx system generator