登录
首页 » VHDL » IIC slave controller source code

IIC slave controller source code

于 2022-02-15 发布 文件大小:2.92 kB
0 170
下载积分: 2 下载次数: 2

代码说明:

IIC slave controller source code

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • tuoji_fpga(xp2_8)_v2
    特大好消息,这是LED全彩控制卡的FPGA的源程序,做LED开发的,绝对有很好的价值(Big good news, this is full-color LED control card FPGA of the source, do LED development, the absolute value of good)
    2010-07-19 16:18:27下载
    积分:1
  • ds1820
    基于FPGA的温度控制系统 VHDL 数码管显示温度 ds1820 温度报警(The temperature control system based on FPGA VHDL digital display temperature ds1820 temperature alarm)
    2015-01-06 14:08:43下载
    积分:1
  • freq_meter
    FPGA的测频程序,用了D触发器,能测1hz到几百hz(FPGA frequency measurement procedures, using a D flip-flop, can be measured to a few hundred hz 1hz)
    2016-04-03 13:41:48下载
    积分:1
  • ethernet_mii_udp_1
    说明:  Verilog开发的,MII接口的百兆以太网UDP代码(100 megabit Ethernet UDP code of MII interface)
    2020-03-20 16:19:21下载
    积分:1
  • FPGA
    说明:  基于FPGA的数字式相位测量仪的设计与制作(FPGA-Based Digital Phase Meter Design and Production)
    2010-04-16 19:40:41下载
    积分:1
  • 鸟哥的Linux私房菜——基础学习篇(第四版)
    全面了解Linux系统,构建服务器,用Vim写写程序(Fully understand the Linux system, build the server, write programs with Vim.)
    2018-11-02 10:56:59下载
    积分:1
  • 基于VHDL的I2C程序0003,很不错的论文及程序,,大家快下啊
    基于VHDL的I2C程序0003,很不错的论文及程序,,大家快下啊-based on the I2C procedures VHDL 0003, a very good paper and procedures, we quickly under ah
    2022-03-21 08:29:16下载
    积分:1
  • chengxu
    数字时钟,可以实现(1) 显示日期功能(年、月、日、时、分、秒以及) (2) 可通过按键切换年、月、日及时、分、秒的显示状态 (3) 可随时调校年、月、日或时、分、秒 (4) 可每次增减一进行时间调节 (5) 可动态完整显示年份,实现真正的万年历显示 (6) 可显示温度 (Digital clock, can be achieved (1) the date function (year, month, day, hour, minute, seconds as well) (2) through the key switch the year, month, day in a timely manner, minute, second display state (3) at any time adjust the year, month, day or time, minutes, seconds (4) can be added or deleted, a time adjustment (5) can be dynamically complete display Year, the real calendar display (6) to display temperature)
    2012-10-15 00:25:33下载
    积分:1
  • at96
    isa总线接口,可以实现与isa总线 的IO和MEMERY接口(isa bus interface can be achieved with the isa bus IO interfaces and MEMERY)
    2008-05-15 20:36:51下载
    积分:1
  • EDA VHDL modules commonly used procedure, the time
    EDA中常用模块VHDL程序,不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ,25分频=2HZ,10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)
    2022-07-02 21:52:46下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载