在vhdl开发环境下，关于协议PS2 verilog 源码

基于FPGA的视觉电生理图像刺激系统的设计(Based on the design of FPGA visual electrophysiology image stimulation system)

signaltap 中文说明，内容详细。 ALTERA signaltap USER GUIDE IN CHINESE(ALTERA signaltap USER GUIDE IN CHINESE)

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说明：  用于实现FPGA硬件开发使用的加法器，需要注意的是用Verilog语言实现的(The adder used to realize FPGA hardware development needs to be realized in Verilog language)

Conduct a digital system ( electronic lock ) using hierarchic methodology . An electronic lock is a device that allows access or opening of a system , as long as the key or combination to enter match with which it is predefined in said lock .

说明：  分数时延FIR滤波器FPGA设计的相关资料及软件无线电实验平台MFSS6842使用说明(Fractional delay FIR filter FPGA design related information and software radio experimental platform MFSS6842 instructions)

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State.Machine.Coding.Styles.for.Synthesis（状态机，英文,VHDL）-State.Machine.Coding.Styles.for.Synthesis (FSM, English, VHDL)

LDPC码不同码率对比，1/2与1/3码率对比。码长512.迭代次数50次。(Comparison of different rate of the LDPC code, 1/2 compared with the 1/3 code rate. 512 yards long. 50 times the number of iterations.)

键盘输入串口输出显示字符,通过串口显示键盘输入的字符-Keyboard input serial output display characters, the keyboard input through serial display characters