DAC verilog 的 Termometric 代码

说明：  计算机组成原理实验多时钟周期CPU设计，包含VHDL代码的设计，实验电路图，实验详细截图。(Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.)

System Generator

数字钟电路的实现，可以24小时计时，可调整时间！(Digital clock circuit implementation, a 24-hour timer, adjustable time!)

VGA 640x480 driver in verilog

vhdl状态机设计,文件简单详细易懂，可以使用在交通灯，文件配置等系统上。(vhdl state machine design, simple, detailed and easy to understand, you can use the traffic light system file configuration file.)

基于VHDL的数字计时器，手动可控正计时和倒计时(含复位键和使能键)(VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key))

基于veilog语言的交通灯控制系统，无左转灯，自制数字电子技术课程设计，仿真通过，由于是多个程序拼接外加本人水平有限，可能结构略有杂乱。

采集外部设备的电压值，用FPGA内部自带的XADC(Collect the voltage value of the external device and use the internal XADC of the FPGA)

实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构-Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure

实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)