Verilog模块的缓存设计

Synthetic Aperture Radar (SAR) imaging simulation target, Using wavelet denoising thought, LCMV optimization design array signal processing.

说明：  viterbi decode by verilog

基于Verilog的小波滤波器程序设计的总结文档。(Verilog based wavelet filter program design summary document.)

基于FPGA的键盘PS第二类编码方式的verilog解码程序。基于FPGA的键盘PS第二类编码方式的verilog解码程序。(FPGA keyboard PS encoding the verilog decoding procedures. FPGA keyboard PS encoding the verilog decoding procedures.)

WOLA polyphase filter加权跌接累加FFT信道化技术(WOLA polyphase filter bank)

verilog触发器，属于数字电子技术实验入门的资料。

基于FPGA的RS编码器设计，verilog hdl语言。(RS encoder FPGA-based design, verilog hdl language.)

说明：  I2C完整代码，可综合，可仿真，已经过验证(I2C code can been syn and simulation ,veritify)

time to digital convertor

基于VHDL语言的波形发生器编程设计，能够实现常用波形的产生。(Waveform generator design based on VHDL programming, to achieve common waveform generated.)