脉动进位加法器

VLSI based question set

Verilog HDL语言编写的汉明编码及解码器，附有时序仿真文件(Verilog HDL language encoding and decoding Hamming, with timing simulation file)

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

说明：  实现在屏幕上显示绿色和红色相间的水平条纹。其中，vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)

一些常见的小模块，自己写的，可能不是特别好，仅供参考，主要是分频器、计数器和数码管的显示

vhdl programming from beginner level

一种基于FPGA的CPU设计-FPGA-based CPU design ........

自动计算fir滤波器系数的工具，不妨一试(Automatic calculation of filter coefficients fir tools, try)

iic的代码，是工程文件来的，是XILINX的，来自开源的-IIC

说明：  基于FPGA的串口发送和接收，使用的verlilog语言(Using Verilog serial port program, send and receive.)