组合电路与时序电路的 VHDL 代码

freeDev数字应用开发板中的七段数码管的IP核的verilog实现-freeDev digital application development boards in the seven-segment digital tube of the IP core implementation of the verilog

数字密码锁的vhdl实现，包括设置密码，修改密码，报警。

它工作斯巴达。 使用 xilinx ise 在斯巴达 6e 效果很好

verilog开发FPGA，实现RS485串口通信(RS485 driver for FPGA )

fpga控制led灯的闪烁，内容简单，希望对初学者有用.(fpga control led lights flashing, the content is simple, I hope useful. . .)

使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。(Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm.)

matlab用法 主要用于线性规划，非线性规划，解决优化问题，作出最合理的决策等遗传算法程序(matlab usage is mainly used for linear programming, nonlinear programming to solve optimization problems, make the most rational decision-making, genetic algorithm)

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

RS码的FPGA实现，verilog语言形式，好参考资料(FPGA realization of RS code, verilog language form, a good reference)

本例为DAC0832接口电路VHDL原代码-The DAC0832 Interface Circuit Example for VHDL source code