freeDev数字应用开发板中的七段数码管的IP核的verilog实现

MD5 算法在Xilinx FPGA上的实现，希望对大家有用。(MD5 algorithm in Xilinx FPGA Implementation, in the hope that useful to everyone.)

自适应滤波器算法LMS ，的FPGA实现，采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)

lacp代码，可以参照学习Lacp协议的相关状态机等知识(LACP code, can refer to the relevant state machine learning knowledge of Lacp protocol)

关于ALTERA DE2板上的文档资料，包括应用实例，用户文档和板上常用器件的技术文档(datasheets of ALTERA DE2)

在FPGA上实现声卡接口，电子琴，滤波比较器，最终实现语音通信 -In the FPGA to achieve the sound card interface, flower, filter comparators, the eventual realization of voice communications

说明：  希望对VHDL的学习大家有帮助，望大家指出错误，浮想交流！(We want to learn VHDL help, hope you point out an error, daydreams exchange!)

使用vhdl实现的1024点的FFT算法-Using vhdl implementation of the 1024-point FFT algorithm

VHDL 2008 A reference book on VHDL-VHDL 2008 A reference book on VHDL

LED灯、跑马灯的显示源程序，包括对代码的说明(Display source code LED lights, marquees, including the code specification)

256字节深度的RS232串口程序,共分4个模块,顶层文件FIFO程序串口收和串口发.经过测试已用于产品.可靠!-Depth of 256-byte Serial RS232 procedures, divided into four modules, top-level document procedures FIFO serial and serial-fat collection. After the test has been used in products. Reliable!