黑金Alinx开发板DDR2读写控制器

使用VHDL语言实现了FPGA与DAC5688进行SPI通信更改寄存器值(The FPGA using VHDL language with the DAC5688 SPI communication to change the register value)

Verilog投币式手机充电仪 清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger EDA major homework of digital electronic technology foundation course, Tsinghua University. Just put on the digital tube completely extinguished, press the start button, the digital tube display is 0. Enter a certain amount, the digital tube shows the amount of double the corresponding time, according to the confirmation began countdown. The maximum amount of input is 20. If there is no button in 10 seconds, the digital tube will die out.)

基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)

PCI arbi verilog source code

说明：  资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序，multifre1.vhd是倍频程序，multifre1.vwf是仿真波形文件，stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用，可以设置倍频数，修改实体参数N即可。(According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe that the procedure multiplier number, multifre1.vhd is the multiplier process, multifre1.vwf is the simulation waveform files, stp1.stp a virtual logic analyzer signaltap file. The multiplier process can be used directly, you can set the multiplier number, modify the parameter N can be solid.)

说明：  关于usb调试相关测试 代码，用于测试和适配等(usb coding for testing , verigy, for studing usb and fpga)

CSS配合jquery制作完美漂亮的时钟，貌似在IE8下时钟不能获取时间啊！支持ie9、chrome、safari、firefox、opera （Chrome显示效果最佳，IE9下时钟无法工作）日历和骰子是原创，CSS3时钟并非原创但经过改良支持opera。数字日历的兼容性不错，圆形时钟就差点了，也希望一起交流，共同改进。(CSS with the jquery make perfect beautiful clock, seemingly in IE8 under the clock can not get the time ah! Support ie9, chrome, safari, firefox, opera (Chrome show the best results, the clock does not work under IE9) calendar and dice is original, CSS3 clock is not original but after improved support opera. Digital calendar compatibility is good, almost round the clock on, and also hope together, and work together to improve.)

通信中加扰/解扰算法。FPGA源代码，verilogHDL语言实现，包含测试程序。(Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.)

shift example for verilog

DLP Discovery 4100 数字微镜(DMD)空间光开关光调制器开发系统 1.全面兼容德州仪器TI DLP D4100 开发系统. 能够支持1920X1080 DMD(DMD微镜为10.6微米,本征分辨率为1920X1080) 数字微镜(DMD)空间光开关光调制器开发系统 2. 1024 X 768 的DMD(4:3)有两种微镜结构，一种是13.68 微米， 对角线长度为0.7 英寸；另一种是10.8 微米的，对角线长度为0.55 英寸；我们系统都能支持所有主流分辨率DMD 3. 支持USB2.0 高速度传输图片和控制信号 4. 开放式控制软件基于Windows XP 全速度USB驱动,在Visual Basic 下编制,开发式接口, 易于高精度光学科研实验 5. 提供丰富的Windows XP 的USB 控制程序和API 开发系统 6. 支持XGA, 1080p 和1920x1200 分辨率单个微镜精确控制 7. 开放式FPGA 架构, 提供示例FPGA 的二次开发选择和客户 定制功能 8. 高速二进和任意灰度制图片显示 输入输出系统触发,支持通 用客户顶GPIO 口设置. 9. 我们能为客户提供全程独特定做和设计服务. 应用: 结构光投影,激光全息,无掩模光刻,高光谱成像,激光光束校形, 3D 测量和3D 打印机技术, 光谱分析. Jefferson_zhao@163.com(DLP DMD Discovery 4100)