四种亮灯方式自由切换的跑马灯(用verilog_hdl语言编写的跑马灯程序)

该实验完成的功能是STM32与FPGA通信(The function of the experiment is STM32 and FPGA communication)

产生高斯最小相移键控信号的阐述仿真，包括调制解调、信道模型等。(Simulation program to realize GMSK transmission system)

adpcm .c程序代码，完整,通过编译仿真(ADPCM c program code, complete compiled simulation)

This is the Spartan 3E tutorial_02.

讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果(described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output)

此代码是由FPGA产生SPWM波的代码，简单易懂(use FPGA to generate SPWM)

代码用两种方法设计了一个基于多相滤波的内插器，低通滤波器采用128阶凯撒窗，内插倍数32，并且给定信号范围，验证了内插器的正确性，画出了内插前后信号的频谱。(The code design the interpolator based on polyphase filter using two methods.The low pass filter is 128 order Caesar window and interpolation multiple is 32.I give the range of the signal to verify the interpolator and plot the spectrum of the signal before and after the interpolator. )

在体系结构中目前为加法器和乘法器在 verilog 和节奏 45nm---报表表与代码 (verilog)---引用 vlsidsp 的 parhi 进行了模拟 这完成由自己 charantej — — 9524435535

fifi asyncronous and syncronus

Efficient CIC filter Implementation using VHDL