usb接口系统设计实例

// 4 entry deep fast fifo module fifo4(clk, rst, clr,  din, we, dout, re, full, empty); parameter dw = 8; input clk, rst; input clr; input   [dw:1] din; input we; output  [dw:1] dout; input re; output full, empty; //////////////////////////////////////////////////////////////////// // // Local Wires // reg     [dw:1] mem[0:3]; reg     [1:0]   wp; reg     [1:0]   rp; wire    [1:0]   wp_p1; wire    [1:0]   wp_p2; wire    [1:0]   rp_p1; wire full, empty; reg gb; ///////////////////////////////////

基于FPGA的VGA控制器，可在屏幕显示彩色条纹(A vga controller based on FPGA)

采用uvm-1.1d system verilog lib uvm可用于大规模仿真验证测试 配套example code提供了从入门级到深入学习的code，在modelsim 10.2c版本上运行成功了

VHDL 波形防止抖动程序,学习试验材料(VHDL prevent jitter waveform procedures, the pilot study materials)

2ask调制与解调的源代码，经过测试可用(2ask modulation and demodulation source code is available, tested)

基于RGMII的UDP网络数据通信，学习FPGA的千兆以太网通信(RGMII based UDP network data communication, learning FPGA Gigabit Ethernet communications)

DDS VHDL include everything of dds AD9914

MATLAB to HDL Code conversion

fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)

Actel FPGA A3P600最小系统原理图，包含JTAG 、电源和封装 (Actel FPGA A3P600 minimum system schematics, including JTAG, power and packaging)