进位保存加法器

用vhdl实现的booth算法乘法器，包含了multiplexer和rca adder，同时提供了一个测试文件，modelsim测试通过(Algorithm with a booth multiplier vhdl implementation, including a multiplexer and rca adder, while providing a test file, modelsim test pass)

说明：  用FPGA完成256*8的存储器的读写操作( complete reading and writing 256* 8 memory with FPGA )

基于VHDL编写的10进制显示输出，基于16进制的10进制控制，适合初学者(VHDL-based display output written in decimal, hexadecimal, 10 hexadecimal-based control, suitable for beginners)

用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)

AHB to Wishbone memory interface VHDL source code

DS18B20温度模块，LCD1602显示(DS18B20 Temperature Module, LCD1602 Display)

CCD图像的颜色插值算法研究及其FPGA实现方法(Color CCD image interpolation algorithm and its FPGA implementation)

ds1302时钟驱动程序，已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)

ise平台模拟UART，并与PC机实现收发（+1）(ISE platform simulation UART and transceiver.)

通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)