改进的DCT算法设计，veriloghdl实现

16 bit switch input view in hexa format on 7seg display

verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the

使用ALTERA上DE2平台，使用Verilog描述，交通灯控制。-Using ALTERA on DE2 platform, use the Verilog description of the traffic light control.

说明：  demo6 蜂鸣器实验 蜂鸣器演奏音乐(demo6 buzzer buzzer experiment playing music)

LDPC COded OFDM System

一个时钟程序，还有跑表，感觉相当不错的，有需要就下载吧-A clock procedures, as well as stopwatch, I feel pretty good, there is a need to download it

FPGA时序分析说明。对于高速时钟设计中的时序分析与约束有帮助(FPGA,TIME)

A simple sequential lights

parity encoder test bench

关于LDPC解码的verilog程序，包含设计代码和验证环境(LDPC decoding on verilog procedures, including the design code and verification environment)