改进的DCT算法设计，veriloghdl实现

vhdl 加法器 vhdl 加法器 vhdl 加法器-vhdl　adder vhdl　adder vhdl　adder

基于FPGA的电子密码锁的设计，内有Verilog HDL源码和各仿真图像-FPGA-based design of electronic locks, which have Verilog HDL source code and the simulation image

对视频编解码芯片ADV7181进行合理的配置，使其输出符合ITUR656标准的视频流-Of the ADV7181 video decoder chip for a reasonable configuration, so that the output in line with the standard video streaming ITUR656

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟(Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock)

VHDL版的C51核(MC8051)-VHDL version of the C51 core (MC8051)

VHDL语言实现VGA的显示彩条横条九宫格的功能。(VGA display color of the VHDL language bar Jiugongge function.)

利用FPGA实现QPSK数字调制。编程采用Verilog HDL语言。(By using the FPGA realization of QPSK digital modulation. Use Verilog HDL language programming. )

本书是一本关于VERILOG方面的专业书籍，是通往FPGA设计的基础书籍，值得一看。(thsi is a book of VerilogHDL,also a basic book to master.)

dct and idct vhdl code

用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)