-
ram_2
简易双口ram,使用两个ram ip core,一个写的同时另一个读,并且包含按键使能和数码管以及流水灯显示(Simple dual-port ram, two ram the ip core, a write while another read, and contains buttons to enable digital pipe and the water light show)
- 2012-07-08 13:05:27下载
- 积分:1
-
05_fifo_test
说明: FIFO: First in, First out 代表先进的数据先出,后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO,根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)
- 2021-04-08 22:19:20下载
- 积分:1
-
5.7
设计一个简单的FIR滤波器,并按要求确定滤波器的系统函数。(Design a simple FIR filter, and determine the filter according to the requirement of system function.)
- 2015-04-17 18:26:49下载
- 积分:1
-
基于verilog的LU分解LUdecompose
基于verilog的LU分解,本文件包括详细的程序代码,运行文件,以及详细的文档(LU decompose based on verilog)
- 2020-07-07 12:58:57下载
- 积分:1
-
gps_lms
本系统用于GPS中频部分的窄带滤波(AD后的数据经过LMS滤波后去掉窄带干扰,可以抑制20dB以上的干扰)(this system can be imply to anti-narrowband-jamming for GPS IF signal, it can degrade 20dB narrowband jamming)
- 2011-08-23 21:06:41下载
- 积分:1
-
uart
说明: uart 发送模块接收模块及tb,其中可以选择不同波特率进行收发,代码带有详细注释。(UART sending module and receiving module)
- 2020-06-20 20:00:02下载
- 积分:1
-
vhdl adder with two input 4
vhdl adder with two input 4-bit and output of 4 bits and carry
- 2022-11-16 00:35:03下载
- 积分:1
-
-
- 2022-03-20 08:41:04下载
- 积分:1
-
fftverilog
关于FFT实现的Verilog代码,(FFT realize on the Verilog code,)
- 2008-02-28 14:02:22下载
- 积分:1
-
DE2 SOPC LCM
DE2 S O P C 用硬件语言 描述地 开发板上测试 CLM模块 实现视频传输-DE2 SOPC LCM
- 2022-07-01 11:31:51下载
- 积分:1