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ZHWX
DDS
产生正弦信号,OOK,AM三种波形。
使用xilinx FPGA VHDL(DDS.
Resulting in sinusoidal signal, OOK, AM three waveforms.
Using xilinx FPGA VHDL.)
- 2016-09-23 16:01:04下载
- 积分:1
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true_dpram_sclk_v-and-readme
Dualport Ram access read and write
- 2020-08-17 14:38:23下载
- 积分:1
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fpga
电子密码锁的相关程序,很好很耐用!但水平有限啊!!(Electronic combination lock procedures,
)
- 2010-12-20 21:51:05下载
- 积分:1
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viterbi
维特比译码,卷积编码,verilog编写,2,1,2编码(Victor than decoding, convolution code, verilog write, 2,1,2 coding
)
- 2011-12-08 23:10:45下载
- 积分:1
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ssi_tx
VHDL同步串口发送部分,基于Xilinx ISE的编程平台(synchronous serial port sending part on VHDL)
- 2021-01-18 20:08:43下载
- 积分:1
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en.SPI_EEPROM_Verilog_models_V10
spi接口的eeprom模型,型号为st公司m65pxx(The eeprom model of spi interface is st company m65pxx)
- 2021-01-19 14:28:44下载
- 积分:1
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mipiTolvds
mipi转LVDS接口, verilog代码,在lattice 芯片上使用,已验证(MIPI to LVDS interface)
- 2018-07-06 20:19:54下载
- 积分:1
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SMBus
SMbus通讯协议的Verilog程序段,已通过Moldesim的仿真,可用(Verilog program segment of the SMbus communication protocol, has been through the Moldesim simulation, the available)
- 2021-03-24 18:29:15下载
- 积分:1
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Double_Pulse_Test
利用VHDL语言描述出一个双脉冲,可任意设置两脉冲长和中间时间间隔。(A double pulse is described in VHDL language, and the two pulse length and the intermediate time interval can be arbitrarily set.)
- 2020-11-22 12:29:35下载
- 积分:1
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GFverilog-hdl
伽罗华域的乘法器的设计,使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)
- 2011-05-01 13:19:22下载
- 积分:1