FPGA内部实现数据大小排序方法

在Qaurtus环境下用Verilog输入实现64QAM信号的发生，用MATLAB协助验证，观察了PN序列对应的星座图。(Simulating generation of 64QAM RF Signal in Quartus II IDE,identified with MATLAB,constellation gram displayed.)

floating point alignment

采用xilinx的ROMIP核产生类似正弦信号，经过FFt后可以观察结果(Using the xilinx ROMIP nuclear generating similar sinusoidal signal can be observed through the results after FFt)

这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)

基于软输出固定复杂度球形译码的高效迭代检测算法，最新的球形译码论文(Iterative detection algorithm based on a fixed complexity soft-output sphere decoding efficiency, sphere decoding papers)

4位ALU,有两个4位输入，4位输出实现逻辑运算和算术运算，逻辑与或非，加1，减1等等功能(4 ALU, logical and arithmetic operations)

this file is vhdl code of alu

利用VHDL语言实现地铁售票系统的设计。售票系统根据途经站数自动计算票价(Using VHDL language metro ticket system. Ticketing system automatically calculated according to the number of fares via station)

一个开源mips处理器verilog 源码(wishbone interface wishbone interface)

基于fpga的计数器模块 分频 可移植 完美实现(Perfect realization of frequency division and portability of counter module based on FPGA)