FPGA内部实现数据大小排序方法

DDS 产生正弦信号，OOK，AM三种波形。 使用xilinx FPGA VHDL(DDS. Resulting in sinusoidal signal, OOK, AM three waveforms. Using xilinx FPGA VHDL.)

Dualport Ram access read and write

电子密码锁的相关程序，很好很耐用！但水平有限啊！！(Electronic combination lock procedures， )

维特比译码，卷积编码，verilog编写，2,1,2编码(Victor than decoding, convolution code, verilog write, 2,1,2 coding )

VHDL同步串口发送部分，基于Xilinx ISE的编程平台(synchronous serial port sending part on VHDL)

spi接口的eeprom模型，型号为st公司m65pxx(The eeprom model of spi interface is st company m65pxx)

mipi转LVDS接口， verilog代码，在lattice 芯片上使用，已验证(MIPI to LVDS interface)

SMbus通讯协议的Verilog程序段，已通过Moldesim的仿真，可用(Verilog program segment of the SMbus communication protocol, has been through the Moldesim simulation, the available)

利用VHDL语言描述出一个双脉冲，可任意设置两脉冲长和中间时间间隔。(A double pulse is described in VHDL language, and the two pulse length and the intermediate time interval can be arbitrarily set.)

伽罗华域的乘法器的设计，使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)