自己做的乘法累加器的verilog代码，移植性强

DE2-115 + D5M Camera to VGA PC

这是一个基于Quartus2 开发环境的4输入加法器( 4adder basic on Quartus2)

实现米粒状态机 用verilog语言实现状态机的过程(Implement a state machine with a grain of rice verilog state machine language course)

说明：  基于VHDL出租车的设计，实现开动、停止的收费功能。(VHDL-based cab design, implementation and running, stop the charging function.)

基于FPGA设计的经典打砖块小游戏。游戏简单易玩。(FPGA design based on the classic Arkanoid game. Game easy to play.)

此应用描述了步进式发动机控制器， 你可以控制发动机

以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)

用verilog实现64点，128点，256点的fft(64 points, 128 points, and 256 points FFT are implemented with Verilog)

231卷积码的verilog实现，前面是详细的文档说明，有源程序，绝对原创！！！！(Verilog achieve 231 convolutional code, preceded by a detailed description of the document, the source, the absolute originality! ! ! !)

It s Flicker_LED code.Verilog for MaxV.