this is the for a equiripple filter

说明：  编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法(Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange)

说明：  本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)

基于FPGA DE0以及niosII的射频无线发送程序,采用spi接口操作无线模块nrf24l01(To spi interface operation wireless module nrf24l01 of FPGA DE0, as well niosII RF wireless transmitter program)

Advanced FPGA Design - Architecture, Implementation, and Optimization(Advanced FPGA Design- Architecture, Implementation, and Optimization)

高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)

Testbench 不仅要产生激励也就是输入，还要验证响应也就是输出。当然也可以只产生 激励，然后通过波形窗口通过人工的方法去验证波形，这种方法只能适用于小规模的设计(The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce Incentive, and then the waveform by the waveform window by artificial means to verify, this method is only applicable to small-scale design)

early branch rename table(store rename table once the branch instruction comes in. Used in out of order pipeline processor)

alter FPGA，包含sdram的nios系统开发实验完整工程文件-nios develop based nios IDE6.0，system involved an sdram

adding custom ip EDK

verilog编写实用多功能电子表-Verilog prepared practical multi-function electronic Table