ALTERA 的关于对SDRAM控制器操作的verilog相关程序，很不错绝对值得借鉴。...

Xilinx 公司Spartan-6系列FPGA实现LVDS，带Modelsim仿真文件，已综合。(Xilinx Spartan-6 Series FPGA implements LVDS with Modelsim simulation file, which has been synthesized.)

说明：  qpsk的fpga实现，包含调制和解调部分，使用verilog语言(FPGA implementation of QPSK)

code for fft non synthesisable in xilinx ise

IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY

对ccd图像进行解码采集，并通过VGA输出(Ccd image decoding of the collection, and through the VGA output)

verylog语言编程，为异步flipflop的程序。具有数据传输功能，数据位数可以用户设定(verylog language programming for asynchronous Flipflop procedures. With a data transmission function, data can be user set the median)

这是用verilogHDL写的m序列发生器，简单易用，代码非常易读(It is written verilogHDL m sequence generator, easy to use, the code is very easy to read)

FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告(FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language)

改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )