多进制数字频率调制(MFSK)系统VHDL程序

fir filter design using vhdl codes

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟(Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock)

数字电子钟用自拍图像代替了内置图像的石英制作

The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last

中值滤波算法的verilog实现，可用于相关算法在基于FPGA的嵌入式图像处理系统中。(Median filtering algorithm verilog realization available FPGA-based embedded image processing system.)

说明：  matlab code for JTAG cable checking

为了便于计算结果在FPGA中后续的计算和ip核中的调用，本代码输入信号为普通浮点型数据，输出为32位表示的浮点型数据。

控制三相步进电机及光电编码器的采集,当电机停止时,保证三相里面只有一相相通,防止停止时电流过大.(Control three-phase stepper motor and optical encoder collection, when the motor stops to ensure that only one phase of three-phase inside the heart, and to prevent too much current is stopped.)

使用uaf42设计的有源滤波器，高通滤波器的设计参数记录(Using uaf42 design active filters, high-pass filter design parameters recorded)

单片机和FPGA的通信程序，发送5个数，传输稳定，可以自行修改可一次传多个数(MCU and FPGA communication program, send five the number of stable transmission, you can modify the number may be more than one pass)