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AD_FIFO
简单的Verilog程序,针对音频实验板的AD到DA调通试验,下载执行前请按照自己试验环境更改设置(Simple Verilog program for test the AD to DA loop of universal audio test platform.
Please configure it according to the test environment before download and implement the program to FPGA)
- 2013-01-26 00:47:37下载
- 积分:1
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GFverilog-hdl
伽罗华域的乘法器的设计,使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)
- 2011-05-01 13:19:22下载
- 积分:1
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IIC slave controller source code
IIC slave controller source code
- 2022-02-15 09:45:19下载
- 积分:1
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SD_rtl
用verilog实现sd卡读写,亲测可用(Implementation of SD card read and write with Verilog)
- 2020-12-27 21:49:02下载
- 积分:1
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VerilogHDLshejifengpingqihe32weijishuqi
本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.(This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.)
- 2007-01-14 17:33:50下载
- 积分:1
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telephone-cost-metering
该程序用来实现电话计时以算取费用,比较简单(telephone cost metering verilog code)
- 2013-11-03 19:45:00下载
- 积分:1
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用Actel公司的Fusion系列FPGA开发的LCD实验程序
用Actel公司的Fusion系列FPGA开发的LCD实验程序-Fusion with Actel s FPGA development series LCD Experimental procedures
- 2022-03-18 21:57:28下载
- 积分:1
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摘要:本文主要介绍以CPLD 芯片进行十字路口的交通灯的设计,用CPLD 作为交通灯控制器的主控芯片,采用VHDL
语言编写控制程序,利用CPLD的可重复编...
摘要:本文主要介绍以CPLD 芯片进行十字路口的交通灯的设计,用CPLD 作为交通灯控制器的主控芯片,采用VHDL
语言编写控制程序,利用CPLD的可重复编程和在动态系统重构的特性,大大地提高了数字系统设计的灵活性和通用性。
关键词:CPLD;VHDL;交通灯控制器
中图分类号:TP39
Abstract :This paper introduces the electronic-traffic lamp, which is based on the VHDL and is completed by-Abstract: This paper introduces the CPLD chip to the traffic lights at the crossroads of design, traffic lights with CPLD as the master controller chip, the use of VHDL language control procedures, the use of CPLD re-programming and dynamic system reconfiguration in the features greatly enhance the digital system design flexibility and versatility. Keywords: CPLD VHDL traffic lights controller CLC number: TP39 Abstract: This paper introduces the electronic-traffic lamp, which is based on the VHDL and is completed by
- 2022-05-20 22:55:36下载
- 积分:1
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XDS100v3-Design-Kit-1.0-Setup
压缩包是ti xds100v3 Design kit的安装文件,安装后有原理图、PCB文件,与DSP接口采用FPGA,安装后有源码,是VHDL格式的,支持开源,降低开发成本(Compression package is ti xds100v3 Design kit installation file after installation schematics, PCB files, and DSP interface with FPGA, after installation source is VHDL formats, support for open source, reduce development costs)
- 2014-08-28 09:36:34下载
- 积分:1
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Verilog HDL__.rar a brief tutorial, very useful
Verilog HDL__.rar
简要教程,很有用-Verilog HDL__.rar a brief tutorial, very useful
- 2022-09-27 05:05:03下载
- 积分:1