vhdl子程序，本人收集的，比较常用的代码

说明：  一个编码解码系统，其中包含一个信号发生器（用查找表方式实现）、一个m序列生成器（用来编码和解码用）、一个FiFo队列用来做缓存以及用串口方式进行收发读取数据。(An encoding and decoding system, which includes a signal generator (implemented by look-up table), an m-sequence generator (used for encoding and decoding), a FIFO queue for caching, and a serial port for receiving, transmitting and reading data.)

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.

FPGA编程，经过团体奋战完成，全是底层的IIc和sci通信，完整版。(FPGA programming, after groups fight to the finish, all underlying SCI and IIc communication, full version)

该程序描述并且模拟和实现了了一个摩尔有限状态机的功能和作用(The program describes the simulation and the function and role of a mole finite state machine)

说明：  数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)

正弦信号发生器（可扫频）通过验证 正弦信号发生器-Sinusoidal signal generator (which can be swept) through the validation of sinusoidal signal generator

说明：  利用vhdl语言编写的译码器程序，采用两种不同方式(The use of language decoder vhdl program, using two different ways)

说明：  基于蜂鸟E203riscv系统的DMA外设代码(DMA code based on hbird_e203 system)