本项目是基于SR和D触发器的使用vhdl.this是100正确的内容。

说明：  本文档对LTE进行了详细的介绍，是一本LTE入门的好书(This document is a detailed introduction to LTE, is a good book to get started with LTE)

VHDL语言实现时钟程序，用fpga开发板试过后，能够执行-VHDL Pang Sung-wife of mother

基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。-something about turbo。

TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus

Vhdl code for aarithmetic logic unit

VHDL语言实现VGA的显示彩条横条九宫格的功能。(VGA display color of the VHDL language bar Jiugongge function.)

-- M68008 Address Decoder -- Address decoder for the m68008 -- asbar must be 0 to enable any output -- csbar(0) : X"00000" to X"01FFF" -- csbar(1) : X"40000" to X"43FFF" -- csbar(2) : X"08000" to X"0AFFF" -- csbar(3) : X"E0000" to X"E01FF" -- download from www.pld.com.cn & www.fpga.com.cn --- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn

简易环形FIFO的设计、简单异步串行通信接口设计等-verilog

这是我自己写的4人表决器源码，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote four voting machine source code, In xilinx Spartan3E debugging has been successful, with the show to share with you!

基于cycloneIIFPGA芯片Ep2c5t144c8的解调程序，用VHDL语言生成-CycloneIIFPGA chip-based demodulation Ep2c5t144c8 procedures, using VHDL language generation