本项目是基于SR和D触发器的使用vhdl.this是100正确的内容。

floating point divider

基于QUATEUS2的设计一个8位频率计verilog语言编程(The design is based QUATEUS2 an 8-bit frequency counter verilog programming language)

vhdl经典源代码――vga控制，入门者必须掌握-vhdl classical source code-- vga control, beginners must master

说明：  自己收集的quartus2 教程以及vhdl语言教程，和如何在quartus中使用modism仿真 ，希望对大家有用(Tutorial quartus2 own collection, as well as language tutorials vhdl and quartus how to use modism, useful for all of us hope)

source vhdl code of D flipflop logic

基于FPGA的多功能波形发生器,很好的,使用Verilong程序。(FPGA-based multi-function waveform generator, a good use of Verilong program.)

说明：  Objects forming possible solution within original problem context are called phenotypes, their encoding, the individuals within the GA, are called genotypes. The representation step specifies the mapping the phenotypes onto a set of genotypes. Candidate solution, phenotype and individual are used to denotes points of the space of possible solutions. This space is called phenotype space. Chromosome, and individual can be used for points in the genotye space. Elements of a chromosome are called genes. A value of a gene is called an allele. Variation Operators The role of variation operators is to create new individuals old ones. Variation operators form the implementation of the elementary steps with the search space.

AGC(自动增益放大) Verilog代码 设计可以参考(AGC (automatic gain control) can refer to the Verilog code design )

RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。(RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.)

实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)