Verilog 编写的ISP1362的控制器IP核，altera公司DE2系统中的源程序

un controller pi par le langage VHDL xilinx ise design 13.2

用VHDL语言实现QPSK调制功能和解调功能,(Using VHDL language features QPSK modulation and demodulation functions,)

ModelSim的使用如何操作和使用以及安装如何安装

一个用VHDL设计的DDS信号发生器，包括两个pics的仿真结果。

Clock Divider, divfactor of 18

Design FPGA in Labview

1、FSMC全称是静态存储控制器，用来高速操作外部SRAM，NOR，NAND等，广泛用来驱动LCD MCU的FSMC配置在fsmc_nor.c，你也可以查阅相关资料。 2、此例程通过读写外部M29W128，熟悉FSMC的配置以及操作。(1, FSMC stands for static memory controller for high-speed operation of external SRAM, NOR, NAND, widely used to drive the LCD MCU FSMC configuration in fsmc_nor.c, you can also access to relevant information. This routine by reading and writing external M29W128 familiar with the configuration and the operation of the FSMC.)

这是fpga按键消抖的源代码，在很多fpga按键实验中都可以用到，能够进行代码移植。(This is the source code of the FPGA buttons, in many FPGA key experiments can be used, and can carry out code.)

说明：  biss协议源码交流 verilog hdl源码，测试可用(Biss protocol ,achieved by verilog HDL,can be verify using modelsim or other simtools.)

FPGA实现增量式光栅尺正交脉冲解码，基于Verilog(FPGA realization of incremental grating ruler orthogonal pulse decoding, based on Verilog)