这是我的VHDL格式的电子密码锁源程序，请站长审核啊

verilog中调用门级电路的实验程序，实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode

support for Coldfire m5441x processors.

步进电机驱动，32等级速度，带加减速度控制。verilog编写。(step motor driver,32 level speed.)

这是使用VHDL语言编写的密码锁程序,供大家参考-This is the use of the VHDL code lock preparation procedures for reference

MAX531串行DA芯片的VHDL驱动，我应经在实际工程中试验过！-MAX531 serial DA chip VHDL driver, I shall be in the actual project tested!

按键在数字电路设计中经常用到。按键的弹跳现象是数字系统设计中存在的客观问题。按键是机械触点，当接触点断开或闭合时会产生抖动。为使每一次按键只做一次响应，就必须去除抖动。本文对按键的抖动信号进行了分析，并通过计数器的方式完成了消除抖动电路模块的设计-?

verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."

CycloneIV控制采样芯片AD9248-20MHz，VHDL语言(CycloneIV control sampling chip AD9248-20MHz, VHDL language)

VERILOG实现无分频时钟，包括测试文件，经过验证可用(VERILOG is no difference between the frequency of the clock implementation, including test papers, can be used after authentication)

Enhanced Audio Project by Dixie Xue & Wei Zhang -Enhanced Audio Project by Dixie Xue & Wei Zhang