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this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer u...
this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
-this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
- 2022-05-22 09:03:05下载
- 积分:1
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verilog中调用门级电路的实验程序,实现了门级舰模
verilog中调用门级电路的实验程序,实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode
- 2022-10-03 09:10:04下载
- 积分:1
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Verilog module containing a synthesizable CRC function
//* polynomial: (0 1 8)...
Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 8)
// * data width: 8-Verilog module containing a synthesizable CRC function
//* polynomial: (0 1 8)
//* data width: 8
- 2022-08-18 21:19:43下载
- 积分:1
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i2c_master_ip_for_nios
i2c master ip for altera nios, add in qsys
- 2018-03-02 14:50:44下载
- 积分:1
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CU设计
计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计
- 2023-06-25 08:00:03下载
- 积分:1
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ddr_for_controller_and_phy
说明: 这是本人曾经参与的一个DDR controller接口项目,主要是FPGA rtl实现,仅供参考。(This is a DDR controller interface project that I once participated in, mainly implemented by FPGA RTL, for reference only.)
- 2020-12-21 20:59:08下载
- 积分:1
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light
基于FPGA的点灯游戏,完整工程。包括鼠标控制,键盘控制,SVGA显示等(Light game based on FPGA, the whole project which includes keyboard control, SVGA and so on.)
- 2020-08-25 14:08:15下载
- 积分:1
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在SOPC下制作自定义部件(PWM发生器)的源程序,包括硬件描述HDL文件和驱动程序文件...
在SOPC下制作自定义部件(PWM发生器)的源程序,包括硬件描述HDL文件和驱动程序文件-Produced in the SOPC custom component (PWM generator) of the source, including hardware description HDL files and driver files
- 2022-03-19 04:54:11下载
- 积分:1
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sdr
全数字OQPSK解调算法的研究及FPGA实现
论文介绍了OQPSK全数字接收解调原理和基于
软件无线电设计思想的全数字接收机的基本结构,详细阐述了当今OQPSK数字
解调中载波频率同步、载波相位同步、时钟同步和数据帧同步的一些常用算法,
并选择了相应算法构建了三种系统级的实现方案。通过MATLAB对解调方案的
仿真和性能分析,确定了FPGA中的系统实现方案。在此基础上,本文采用Verilog
HDL硬件描述语言在Altera公司的QuartusⅡ开发平台上设计了同步解调系统中
的各个模块,还对各模块和整个系统在ModelSim中进行了时序仿真验证,并对
设计中出现的问题进行了修正。最后,经过FPGA调试工具嵌入式逻辑分析仪
SignalTapⅡ的硬件实际测试,(The Research and FPGA Implement of All
Digital OQPSK Demodulation Algorithms
)
- 2020-06-30 18:00:01下载
- 积分:1
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8位十进制频率计,通过验证,目标芯片EPF10KLC84
8位十进制频率计,通过验证,目标芯片EPF10KLC84-4-8 decimal Cymometer through authentication, the target chip EPF10KLC84-4
- 2022-07-15 16:44:52下载
- 积分:1