xvrware图书馆Xilinx Inc.

8051core-Verilog FPGA

使用Verilog语言对128点 基8FFT的实现(Implementation of 128-point basis 8FFT)

HDL example source code 2/5 dff_en

使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。-use of the VHDL language ALTERA company"s board up3 have vga signal containing a detailed analysis and explanation is a good guide.

基于FPGA的uart控制器，波特率可选，VHDL编程，Quartusii 6.0 平台，vhdl语言编程-FPGA-based UART controller, an optional baud rate, VHDL programming, Quartusii 6.0 platform, vhdl language programming

usb读取，仅供参考，在实际应用中要更改以下数据。(Read usb data)

基于VHDL编写的10进制显示输出，基于16进制的10进制控制，适合初学者(VHDL-based display output written in decimal, hexadecimal, 10 hexadecimal-based control, suitable for beginners)

说明：  CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。(CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write registers, read and write memory and execution.)

2ask调制与解调的源代码，经过测试可用(2ask modulation and demodulation source code is available, tested)

HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)