QPSK fpga程序

利用VHDL语言实现地铁售票系统的设计。售票系统根据途经站数自动计算票价(Using VHDL language metro ticket system. Ticketing system automatically calculated according to the number of fares via station)

基于CPLD芯片EPM570的verilog hdl串口程序(the UART verilog hdl code based on CPLD chip-- EPM570)

一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。(A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.)

SRAM 读写实验，SRAM存储器的读写操作，Verilog源码有助于提高代码coding能力。使用例程。(SRAM write and read)

C源碼16C550 串口驅動，使用中斷收送RS232資料(16C550 UART Driver)

QPSK在赖斯信道下的模拟仿真，包括K=6和K=10下的情况(QPSK in, Laisi Xin Road, under the simulation, including the case of K = 6 and K = 10 under)

自动售货机，根据所要的东西，自动收费，并进行找零(Vending machine, according to what you want to automatically charge and conduct Keep the change)

PC104总线的CPLD代码，调试已经通过，可以修改应用到其他的工程(PC104 bus CPLD code, debugging has been passed, you can modify the application to other engineering 示例用法:)

vhdl例程代码大全，包含流水灯，数码管，AD,DA转换等(Guinness vhdl code routines, including water lights, digital, AD, DA conversion)

Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a station in Power Save mode