DE2115串口收发源码

Verilog实现DDS线性调频，Verilog实现DDS线性调频(Verilog implementation of DDS linear FM，Verilog implementation of DDS linear FM)

使用DDR3IP核进行仿真，写入读取数据(Using DDR3IP core to simulate, write and read data)

binary adder / subtracter in vhdl

FPGA与PC端实现串口数据的收发，先从PC端接收数据，然后发回给电脑，可通过串口助手验证。(The serial port data is sent and received between the FPGA and the PC. First, the data is received from the PC, and then sent back to the computer. It can be verified by the serial port assistant.)

FPGA实现四位数与四位数乘法，有仿真波形，合理利用FPGA资源(Four-digit and four-digit multiplication is realized by using FPGA. It has simulation waveform and makes rational use of the resources of the FPGA.)

SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。(This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.)

基于Verilog的图像采集、处理和存储程序，初学者参考，高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)

说明：  uvm lab代码以及uvm1.2源码，带有使用说明文档，可以照着文档一步一步深入了解uvm代码。(The code of UVM lab and the source code of uvm1.2 are provided with instruction documents. You can follow the documents step by step to understand the UVM code.)

说明：  设计11位巴克码序列峰值检测器，巴克码相关器原理：巴克码相关器能够检测巴克码序列峰值，并且能够在1bits错误情况下检测巴克码序列峰值。(A 11-bit Barker code sequence peak detector is designed. The principle of Barker code correlator is that the Barker code correlator can detect the peak value of Barker code sequence and detect the peak value of Barker code sequence in the case of 1 bits error.)

自适应滤波器是指利用前一时刻的结果，自动调节当前时刻的滤波器参数，以适应信号和噪声未知或随机变化的特性，得到有效的输出,本设计在MATLAB仿真的基础上，使用verilog实现，附带仿真波形图，实用性强