16快速乘法器的VHDL

In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.

《可综合的Verilog语法》国外著名大学老师编写，对于理解verilog HDL文件的可综合与不可综合会有帮助。-synthesizable Verilog syntax and semantics,by teachers from university of Cambridge,It is userful for verilog HDL design.

Xilinx的I2C总线控制器，verilog版本，文档号是XAPP333，可到Xilinx网上查找具体说明，有对应的VHDL版本的-Xilinx

用FPGA实现dct变换。verilog语言实现，在quartus9.0中验证，含整个工程(dct transform verilog language in quartus9.0 verify, with the entire project)

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第三个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The third document

RISC(精简指令集计算机)存储程序状态机的源代码-RISC (reduced instruction set computer) stored procedures source code of the state machine

说明：  Implementing SMPTE SDI Interfaces with UltraScale GTH Transceivers

AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)

交通灯通过数码管显示，几种模式可调，还可以时间可设，适合初学者入门参考学习。(LED traffic lights can be set to several modes adjustable time beginners reference ~ ~ ~)

Disparity mapp code in VHDL