vhdl classical source code

verilog code for counter four

配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)

浮点加法器的用Verilog实现，32位的浮点加法器(Floating point adder Verilog)

此为多功能数字电子钟的vhdl代码，有闹钟、时间可调、计时等功能-This is a multi-function digital electronic clock VHDL code, has an alarm clock, time adjustable, timing and other functions

VHDL由简单存储器，计数器等搭建最终实现8位的cpu设计(VHDL realization 8 of cpu design)

超低速的光纤一体发接收发送器,同于以前的光纤一体化接头都只适用于2M以上的通讯,如需将232等低速信号用光纤传输出,需要加复杂的调制解调电路,网动光电新生产的这款光纤头主要针对低速信号,可以传送DC-500KPS的信号,极大地简化了硬件设计.(Ultra-low-fat whole-speed fiber-optic transmitter receiver with fiber-optic integration in the previous joint only applies to more than 2M communications, etc. For the 232 low-speed optical fiber transmission of signals, the need to increase the complexity of the modulation and demodulation circuit, the net move Photoelectric new production of this first major response to low-speed fiber-optic signal, DC-500KPS can send the signal, greatly simplifying the hardware design.)

FPGA的学习指南，绝对经典，内容比较超值，我已经细心读过了，讲解清晰，快速入门。-FPGA-study guide, an absolute classic, the content of more value, I have carefully read, and to explain clearly, Getting Started.

This is the update firmware for CVFX-C02, 7" motorized touch screen car dvd player gps

基于FPGA的频率相位可调DDS信号发生器-FPGA-based phase adjustable frequency DDS signal generator

xlinx fpga实现fft功能，利用ip核，包含源程序及完整工程文件，直接就能使用(The fft function xlinx fpga ip-core contains the source code and complete the project file, and can be used directly)