vhdl classical source code

H.265的FPGA实现！！使用Verilog语言开发。(H.265 FPGA implementation! Developed using Verilog language.)

SystemVerilog For Design (Springer-2nd_Ed-2006)

this example exchanges the NRZ code to the MANCHESTER code with moore output

一个8位CISC结构的精简CPU，2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler

ＶＨＤＬ语言的一些经典实例源代码，包括状态机，时序电路，组合逻辑电路等(Some classic examples of VHDL language source code, including the state machine, sequential circuits, combinational logic circuits)

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URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)

fpga程序，产生1pps脉冲信号，使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)

说明：  artix 7系列 fpga mig ddr3应用教程(Artix 7 Series FPGA MIG DDR3 Application Tutorial)

PID CONTROLLER HELPING BOOK