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This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...

于 2022-04-07 发布文件大小:2.15 MB

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This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

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This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...

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