This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...

VHDL_COUNTING 时间使用按钮 (Đếm giờ phút giây sử dụng nút nhấn)

说明：  USB主机和设备的verilog代码，实现了USB1.1协议规范的要求(USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements)

this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the main file included in the project.-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the main file included in the project.

nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)

Actel FPGA A3P600最小系统原理图，包含JTAG 、电源和封装 (Actel FPGA A3P600 minimum system schematics, including JTAG, power and packaging)

用VHDL语言编写的串口通讯模块，可以实现发送和接受功能。-A UART module writen in VHDL.

16QAM,64QAM,256QAM调制下的球形译码(16QAM, 64QAM, 256QAM modulation sphere decoding)

很好的NAND Flash 硬件驱动语言，支持VHDL和verilog 语言方便移植，如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。(NAND Flash Controller Reference This reference design is used to interface a NAND Flash device and provides a simple host end interface. The host end interface of this design is user-configurable. It provides buffer select signal, buffer write enable signal, address bus, data bus, error status signal, control and handshake signals for the user......)

该书介绍了英特尔的80x86CPU和一些串行通信芯片，以及汇编语言。(The book introduces the Intel 80x86CPU and some serial communications chip, and assembly language.)

说明：  FPGA按键延时模块，产生key_value和key_flag 可直接例化调用(The key delay module of FPGA)