This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...

FPGA实现SPI接口的从机功能，接收和发送全双工运行，接收到的数据以八位LED灯显示(FPGA to achieve the SPI interface the machine function, receive and send full-duplex operation, the received data to eight LED lights)

Simple vhdl description to show numbers on 7-segment s on Altera DE2 board.

一个任意整数分频程序,采用VHDL语言编写，编译通过-An arbitrary integer frequency procedure for the VHDL language, the compiler through

In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random. To handle this, multipath affected channels require Equalizers at receaver end. such equalizer uses different learning Algorithms for identifying channels continuously. This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.

Programmable IIR Filter written in Verilog and its respective modules.

该源代码是RS（31，19）码的完整编译码程序，采用的是VerilogHDL语言，包含了RS码的编码和译码，这蛋疼的东西花费好多时间(The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this egg pain)

System Verilog for design verification

8251的完整的功能的实现,可以进行编译,综合.-8251 complete function of the realization can be compiled and integrated.

ADC TLC5510的测试程序，经过测试通过，十分简单好用-ADC TLC5510 test procedures, after the test is very simple and easy

fpga串口的接收程序基于verilog语言拿走不用谢。(The receiving program of FPGA serial port is based on Verilog language.)