This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...

说明：  Verilog学习文档，介绍基本知识点，语言要素(for learning Verilog)

此ip核是xvga视频接口控制器，主要针对xilinx公司的开发工具-This ip is nuclear XVGA video interface controller, the main target Xilinx

本程序调试了TI的高精度模数转换芯片ADS1115,此模数转换器采用双积分型，16位，为IIC通信方式，调试较复杂，在对直流采集方面有着广泛的应用(This program debugging TI s high-precision analog-digital conversion chip ADS1115)

实现qpsk解码，适合新手学习，代码简单，好用(mplementation of QPSK decoding)

shift example for verilog

在MATLAB的SIMULINK中，用DSPBUILDER实现计数功能，控制LED指示灯.(In MATLAB SIMULINK, DSPBUILDER is used to realize counting function and control LED indicator lamp.)

包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。(Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.)

This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II assembly language, which run on Altera’s DE2 boards.

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )

VIVADO 从此开始,详细讲解了vivado,FPGA开发工具的使用，对于初学者学习VIVADO工具很有用。(VIVADO from now on, explained in detail the use of vivado, FPGA development tools, for beginners to learn VIVADO tools very useful.)