VHDL数字系统设计工程实践，包含实验的原理，真值表和结构图描述，以及相关的VHDL代码。...

四位乘法器的VHDL源程序-four Multiplier VHDL source

Bone microphnoe simulator. this is a trial to de-noise the bone microphone signals. This also utilizes om-lsa algorithm

利用verlilog hdl语言编程，完成了8051内核，非常值得学习硬件描述语言的人看看！-Verlilog hdl programming language to use to complete the 8051 core, very much worth learning hardware description language of the people to see!

说明：  vcs中文使用教程，帮助你快速入门Linux下的VCS操作(VCs Chinese tutorial to help you get started with VCs operation under Linux)

基于CPLD硬件描述语言编写的五电平SVPWM脉冲触发程序(Five level SVPWM pulse trigger program based on CPLD hardware description language)

verilog 简易频率计的设置，包括整个工程(verilog simple frequency meter settings, including the entire project)

利用VHDL语言编写的4*4键盘扫描程序，经过测试，可以放心使用。(Using VHDL language 4* 4 keyboard scanning procedures, tested, safe to use.)

FPGA控制SRAM读写时序源码，代码桂发，新手一看就懂(FPGA control SRAM write timing source code Guifa novice understand at a glance)

从FPGA输出到HDMI Tx的verilog 模块。实现完整HDMI图像输出功能。(FPGA output to HDMI Tx module in verilog)

当年本科时的毕业设计，信号发生器和频率计-The time of the year undergraduate graduate design, signal generator and frequency counter