LDPC码的消息节点（Bitnode）消息更新过程的VHDL语言实现

基于FPGA设计的一个PID控制系统，完成对物体检测和运动控制；直流电机和步进电机驱动模块是可选的。(PID control system based on FPGA: Objection detection, movement control, motor driver is optional)

使用LPM_ROM的实际的例子-Use of practical examples LPM_ROM

This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)

自己编写的红外解码子程序，但CPU资源占用较高，作教学示范用途。(prepared their infrared decoding routines, but higher occupancy CPU resources for teaching demonstration purposes.)

基于VHDL的电子秒表的设计，使用VHDL语言描述一个秒表电路，利用QuantusII软件进行源程序设计，编译，仿真，最后形成下载文件下载至装有FPGA芯片的实验箱，进行硬件测试，要求实现秒表功能。(Design of electronic stopwatch based on VHDL)

quartus2的中文文档，不是很全，仅供大家学习(quartus2 the Chinese document, not very wide, only for them to learn)

无线通信FPGA设计Matlab Verilog代码(Wireless FPGA design Matlab Verilog code)

Program for simulate a prtsc

开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit

数字频率测量器，脉宽测量器。可测量多种频率波形的脉宽。(Digital frequency measurement device, pulse width measurement device. Measurement of the waveform of frequency pulse width)