LDPC码的消息节点（Bitnode）消息更新过程的VHDL语言实现

用vhdl写的-using VHDL write

it is a filter contract VHDL .(it is a filter contract VHDL.)

Verilog Language Manual

利用Quartus 综合简单的计时器功能，欢迎大家下载、参考。谢谢大家的支持！

The aim of the ECG simulator is to produce the typical ECG waveforms of different leads and as many arrhythmias as possible. My ECG simulator is a matlab based simulator and is able to produce normal lead II ECG waveform.

数字电子琴控制器的ＶＥＲＩＬＯＧ代码，含中文注释．-The number of organ controller Verilog code, with English Notes.

A simple sequential lights

Verilog HDL语言编写的汉明编码及解码器，附有时序仿真文件(Verilog HDL language encoding and decoding Hamming, with timing simulation file)

美国人写的各种类型的fpag设计指导，非常详细的介绍了从fpga的型号，结构，实现，编程，等各个方面的要点。-Written by Americans of all types of fpag design guide, very detailed introduction from the FPGA models, structure, realize, programming, and other aspects of the main points.

对于中断技术有非常详细的讲解，带图片完整版(Technology for the interruption of a very detailed explanation, with pictures full version)