VHDL参数化浮点乘法器

ldpc编码器ru算法的verilog语言的完整实现，希望对您有用(ldpc encoder, RU, VERILOG，altera)

自己编写的verilog语言 PWM实现的一种方法希望有用(verilog PWM)

读取IGS数据中心提供的sinex文件 并恢复法方程(Read sinex file IGS data centers and to restore normal equation)

利用vhdl编写的双端口Ram程序，不带数据纠错处理-VHDL prepared to use dual-port Ram procedures, do not deal with data error correction

在EDA实验课上面，自己编写的NCO程序，可以产生出比较真实的正弦波、三角波以及锯齿波，用VHDL程序编写，有modelsim仿真textbench程序(On EDA experiment, oneself write the NCO program, can produce more real sine wave, triangular wave and sawtooth wave with VHDL programming, have the modelsim simulation textbench program )

Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.-Clock_Dithering_Verilog this is a Clock u_dither, everybody want to make Verilog-jitter can refer to.

实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构(Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure)

Construction and Experimental Evaluations of User-Centered Power

通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)

基于FPGA用verilog语言实现16点FFT(16-point FFT FPGA-based verilog language)