基于FPGA的三相异步电机变频调速程序

uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device

VERILOG比较器设计，属于数字电子技术实验入门的资料。

SPI slave接口协议，基于verilog，调试可用

32-bit Wishbone Interface • DMA • Buffer Descriptor • Compliant with SD Host Controller Spec version 2.0 • Support SD 4-bit mode • Interrupt-on-completion of Data and Command transmission • Write/Read FIFO with variable size • Internal implementation of CRC16 for data lines and CRC7 for command line Wishbine 总线使用。完整的SD卡控制器，支持文件系统，高速传输。

用Vrilog产生一个混沌信号，并用MATLAB仿真，画出波形。(With Vrilog generate a chaotic signal simulation using MATLAB, draw the waveform.)

VHDL 基于cpld EPM570的DA转换代码(VHDL CPLD EPM570 the DA conversion code based on)

交通灯通过数码管显示，几种模式可调，还可以时间可设，适合初学者入门参考学习。(LED traffic lights can be set to several modes adjustable time beginners reference ~ ~ ~)

用verilog编写的信号调制解调程序，包括ask,fsk,qpsk的fpga实现(Prepared using verilog signal modulation and demodulation process, including ask, fsk, qpsk of fpga implementation)

说明：  基于quartus2的jk触发器设计，内含源码和仿真图(Jk flip-flop design based on the quartus2, containing source code and simulation diagram)

资源描述 本设计中可以实现测量周期，测量方波的占空比，被测范围1Hz-100MHz。相对误差小于0.001%. 可以测方波、正弦波等波型。同时还有上下左右按键控制显示