VERILOG比较器设计

用Verilog实现1602的配置及功能。正确编译与实现(Realized by Verilog 1602 configurations and functions. Compilation and implementation of the right)

Multipleksor 3 to 1 - 3x1bit in, 1x1bit out

ＵＣ1698Ｕ驱动160*160ＬＣＤ中文应用及例程(UC1698U driver 160* 160LCD Chinese applications and routines)

FPGA核心板EP4CE10F17C8电路原理图(Circuit schematic diagram of EP4CE10F17C8 core board of FPGA)

用verilog编写的lms算法。可实现自适应滤波功能(Lms algorithm written in verilog. Adaptive filtering can be achieved)

驱动8*8点阵块显示汉字，可以自己根据要显示的内容随意更改，已通过验证。(Blocks of 8* 8 dot matrix drive display Chinese characters, you can display the content according to their random changes, has been verified.)

turbo码在LTE中的实现，并在fpga中得到了实现(turbo code in LTE implementations, and have been achieved in fpga)

红外接收处理，根据外部波形记录波形的高低电平时间，从而得到波形数据。(Infrared receiver processing, according to the external waveform waveform record high and low times, resulting waveform data.)

同步 FIFO 的 Verilog 设计代码。核查 Env 可以围绕它 SV 或 UVM。数据宽度是 8 位和 FIFO 深度是 2 ^3 = 8