A signal can be stretched any one CLk the VHDL source code examples. See documen...

在FPGA EGO1的口袋平台上实现数码管滚动显示学号的功能(Rolling on the digital tube to display the school number)

利用VHDL实现CPLD（EPM240T100C5）的串口发送程序-Using VHDL realize CPLD (EPM240T100C5) Serial sending procedures

Verilog Blocking and Non Blocking

当时是用于课程设计而编写的代码，经过的运行没有错误。精确率很高。基于FPGA的数字频率计VHDL源码（精确到1.1hz至20.0mhz）

VHDL的基本数学运算库,非常好用-VHDL basic arithmetic library, a very handy! !

这个是用VHDL实现FPGA对FLASH的读写。(This is achieved using VHDL FLASH FPGA to read and write.)

this is the vhdl code for the arithmetic logic unit.enjoy!

直接数字式频率合成器DDS设计、Verilog。 产生的信号可以是正弦波或方波、三角波、锯齿波等，自选。 采用DDS技术，将所需生成的波形写入ROM中，按照相位累加原理合成任意波形。 此方案得到的波形稳定，精度高，产生波形频率范围大，容易产生高频。 本实验在设计的模块中，包含以下功能： （1）通过 freq 信号输入需要的频率的值； （2）通过 wave_sel 信号选择所需的波形； （3）通过 amp_adj 信号选择波形放大的倍数。(DDS design of direct digital frequency synthesizer, Verilog. The generated signal can be sinusoidal or square wave, triangular wave, sawtooth wave and so on, optional. By using DDS technology, the required waveforms are written into ROM, and arbitrary waveforms are synthesized according to the principle of phase accumulation. The waveform obtained by this scheme is stable, accurate and easy to generate high frequency waveform. This experiment includes the following functions in the designed module: (1) Input the required frequency value through freq signal; (2) Choosing the required waveform by wave_sel signal; (3) Select the multiplier of waveform amplification by amp_adj signal.)

vedic multiplication

说明：  16点verilog FFT，可供参考学习使用(16 points Verilog FFT can be used for reference)